A substantial industry has evolved for packaging integrated circuit (IC) memory devices into subassemblies, known as memory modules, for use in computing devices. Personal computer manufacturers tend to order assembled and tested memory modules, as opposed to individual memory integrated circuits, for the assembly of personal computers. In this way, computer manufacturers avoid the labor expenses and training needed to assemble and test memory integrated circuits on a memory module before the manufacturer integrates the module into a computing device.
To enhance the ease of assembly and integration of memory modules in computing devices, standards have been developed for interfacing memory modules with computing devices. For instance, a typical memory module has defined interface lines for transferring control information, address information and data information between memory integrated circuits located on the module and a computing device supported by the module. As an example, a typical memory module may have 64 or 72 data lines for supporting data transfer to and from a bank of eight or more memory integrated circuits accessed in parallel, and additional lines for communicating control and address information with the memory integrated circuits. Each integrated circuit has pins that connect the integrated circuit with module lines for communicating control, address, and data information.
The configuration of a memory module, meaning the number, type, arrangement and interfacing of integrated circuits on the module, is not readily apparent through a visual inspection of the integrated circuits loaded on the module. For instance, a given arrangement of integrated circuits may not use all of the available control, address and data lines of a memory module. Further, different types of integrated circuits can use similar module lines but communicate different types of data over these lines. Thus, the configuration of a memory module depends upon end user requirements and the parts used to assemble the memory module, including the type of memory integrated circuits loaded on the module.
Before an end user, such as a computer manufacturer, will generally accept a memory module for assembly into a computing device, the end user usually requires testing of the memory module to ensure compliance with its requirements. Testing of memory modules is accomplished by writing and reading a variety of data to the module to ensure that the module, and the integrated circuits on the module, performs accurately. Such testing is performed based upon the particular configuration of the module being tested. Thus, the first step in testing a memory module is identifying the configuration of the module so that a pre-determined test sequence can be performed on the module.
Conventional memory module testing has relied upon manual entry of test parameters determined according to a visual inspection of the memory module and the parts loaded on the memory module. However, manual entry of test parameters is a time consuming and tedious task that is prone to human error. In particular, manual entry of test parameters is difficult and time consuming when testing a large variety of memory module configurations.
To overcome difficulties associated with manual entry of test parameters, Tanisys Technology, Inc. has led the industry in developing automated systems for identifying the configuration of a memory module. U.S. Pat. No. 5,812,472, entitled "Nested Loop Method of Identifying Synchronous Memories", by Lawrence, et al., and assigned to Tanisys Technology, Inc., which is incorporated herein by reference, discloses a nested loop method for identifying the configuration of a memory module. The nested loop method tests a sequence of bit patterns retrieved from tables representative of memory parts to determine the configuration of a memory module under test. Essentially, the nested loop method identifies a memory module configuration by performing read and write cycles to the memory module under test until the identification of parts on the memory module is accomplished.
Although the automatic identification method and system developed by Tanisys Technology, Inc. provides a significant advance for automatic identification of a memory module configuration to greatly enhance memory module testing, a number of difficulties remain with the nested loop identification method. One difficulty is the time generally used to perform read and write cycles in sequence until identification of the memory module configuration is accomplished. In summary, the nested loop method runs a sequential series of read and write cycles and checks the results of the read and write cycles against a table to identify parts on the memory module. Depending upon the number of parts and the number of cycles run until the parts are identified, the nested loop method can take up to one minute to identify a memory module configuration.
Another difficulty associated with identifying a memory module configuration occurs when the memory module has a defect. For example, during assembly of a memory module, a bad wire or pin connection can result in failure of signal transfers to and from one or more parts loaded on the memory module. If, for instance, a memory bank having nine address lines has a poor pin or wire connection for one address line, then a tester may identify the memory module configuration as a single memory bank having eight address lines. Based upon such an erroneous identification, the tester may test the system as an eight address line configuration, resulting in passing of the test and shipment of a faulty memory module.
Safety is another concern associated with memory testing. Typically, memory module configuration identification is accomplished before testing is performed. However, in order to identify any memory module configuration automatically, power is generally applied to the memory module to support a series of read and write operations. If the memory module has a fault or is erroneously loaded in the tester, powering up of the memory module can result in damage to the module as well as the tester. For instance, a tester operator might load a memory module into a tester backwards. In such a case, application of power from the tester to the module for identifying the module configuration can result in damage to an otherwise operable memory module.